Read-only memory for a gate array arrangement

ABSTRACT

Basic cells (GZ) that are composed of at least three p-channel transistors (TP) and of three n-channel transistors (TN) are employed for constructing a read-only memory. Only the outwardly disposed transistors (TP1, TP2) or, respectively, TN1, TN2) are employed for storing the information, whereas the inwardly disposed transistors (TN3, TP3) are not used. An information is stored in that the gate electrode (G) of one transistor (TP, TN) is connected to a word line (W), the drain electrode is connected to a bit line and the source electrode is connected to a fixed supply voltage (VDD, VSS) or is not connected thereto. The layout of the basic cell (GZ) is executed such that the gate terminals ensue in the inner region of the basic cell and the word lines (W) and bit lines (B) are conducted over the basic cell perpendicularly relative to one another. Read-only memories of arbitrary size can be realized by joining such basic cells in rows and columns.

BACKGROUND OF THE INVENTION

The invention is directed to a read-only memory for a gate arrayarrangement upon employment of basic cells that contain at least onen-channel and p-channel transistor.

Gate array arrangements are known (for example, Hitachi review, Vol. 33,1984, No. 5, Pages 261-26). In such gate array arrangements, cellregions or cells are provided in a defined arrangement on a chip, basiccells being realized thereon. The basic cells are composed of n-channeland p-channel transistors that are arranged in the cell regions. Thebasic cell can be specified for the realization of a basic function byconnecting the n-channel transistors and p-channel transistors per basiccell and, for example, it can be lent a logical function or a memoryfunction.

The individual basic cells in the gate array arrangement must beconnected to one another for setting functions. This then occurs viawiring channels that are conducted past between the lines of basic cellsor over lines of basic cells.

The realization of memories having differing capacity was previouslyachieved in various ways. Bistable circuits were employed for storingstructures having low capacity. These are composed of a plurality ofgates and therefore require comparatively many basic cells of a gatearray for storing an information unit. High-capacity memories wererealized in that a memory having block-defined capacity designed as ageneral cell was integrated in the region of the chip. This led theretothat the capacity of a memory can be selected only in steps of thememory capacity of this general cell (also referred to as macrocell).Finally, the space requirement for such memories was relatively highsince wiring channels had to be arranged between the lines of basiccells.

Read-only memories upon employment of MOS transistors are known (forexample, H. Weiss, K. Horninger, Integrierte MOS-Schaltungen,Halbelektronik 14, Springer-Verlag 1982, Pages 232,233). For storing aninformation unit of the one type, for example "1", a MOS transistor hasits controlled path arranged between a supply potential and a bit lineand has its gate electrode connected to a word line. For storing aninformation unit of the other type, for example, "0", no MOS transistoris arranged at the intersections between bit line and word line. It doesnot derive from the reference, however, how a read-only memory of thisprinciple can be realized in gate array arrangements upon employment ofgiven basic cells.

SUMMARY OF THE INVENTION

The object underlying the invention is comprised in specifying aread-only memory for gate array arrangements whose capacity can beadapted to the respective need and thereby employs basic cells that arelikewise employable for the realization of logic functions or for therealization of other basic functions.

In a read-only memory of the species initially recited, this object isachieved by the features of the characterizing part of patent claim 1.

A basic cell composed of at least six transistors, namely threen-channel transistors and three p-channel transistors, is employed. Fourbit lines and two word lines can then be conducted over a basic cell andfour bits can be stored upon employment of respectively two n-channeltransistors and two p-channel transistors. The programming ensues bycontacting the drain electrodes of the transistors with a bit line, thegate electrodes with a word line and the source electrodes with a supplypotential. This arrangement guarantees that none of the storagetransistors must be operated in source follower mode.

In another embodiment, two transistors are utilized per bit to bestored, namely, a respective p-channel and a respective n-channeltransistor. Two bits can then be stored per basic cell.

The basic cell is preferably realized such that three p-channeltransistors are arranged in a first region and three n-channeltransistors are arranged in a second region lying adjacent to the firstregion. The gate electrodes thereby proceed parallel to one another andthe controlled paths of the p-channel transistors or, respectively, ofthe n-channel transistors lie in series. The gate terminals of the gateelectrodes are arranged between the two regions or lie at the inneredges of the two regions. The supply lines, by contrast, are arranged atthe outer edges of the two regions. The gate electrodes of the p-channeltransistor lying in the center and of the n-channel transistor lying inthe center are connected to one another. Given a basic cell executed insuch fashion, only the two outwardly disposed n-channel transistors or,respectively, p-channel transistors are used for storing information.

Other developments of the invention derive from the subclaims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention shall be set forth in greater detail with reference toexemplary embodiments that are shown in the FIGS. Shown are:

FIG. 1 a first exemplary embodiment wherein four information units arestored per basic cell, comprising output circuit;

FIG. 2 a second exemplary embodiment;

FIG. 3 a layout of the basic cell comprising connections for storingfour information units;

FIG. 4 a third exemplary embodiment of the invention wherein twoinformation units are stored per basic cell per bit line;

FIG. 5 a modified allocation of the information units to the p-channeltransistors;

FIG. 6 an exemplary embodiment wherein two transistors are employed forstoring an information unit and wherein the read-only memory workswithout pre-charging of the bit lines;

FIG. 7 a portion of a gate array arrangement comprising basic cellsaccording to FIG. 3, but without wiring.

DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 yields a first exemplary embodiment upon employment of a basiccell GZ and of an output circuit AG via which bit lines B are connectedto a data line DA. The basic cell GZ comprises two p-channel transistorsTP1 and TP2 and two n-channel transistors TN1 and TN2. These transistorsare used for storing information units, for example, binary "1" and "0".The output circuit contains pre-charging and holding circuits VL, HL andtristate circuits TR.

The bit lines B are connected to a supply potential via pre-chargingtransistors TV. The bit lines Bm+2, Bm+3 to which p-channel transistorsTP are connectible are thereby connected via a p-channel pre-chargingtransistor TVP to a supply potential VSS, whereas the bit lines Bm, Bm+1to which n-channel transistors TN are connectible are connected via an-channel pre-charging transistors TVN to a different supply potentialVDD.

Selection lines W, the word lines, proceed over the basic cell GZperpendicular to the bit lines B. The gate electrodes of the transistorsTP, TN employed for storing are connectible with these word lines.

The P-channel transistors TP are connected to the word line W_(n+1) andn-channel transistors TN are connected to the word line W_(n). Forreading an information out, a lower potential is applied to the wordline W_(n+1) and a higher potential is applied to the word line W_(n),i.e. the word line W_(n+1) is low-active and the word line W_(n) ishigh-active.

In the exemplary embodiment of FIG. 1, a "0" is stored when the gateelectrode of a p-channel transistor TP or of an n-channel transistor TNis connected to the allocated word line W and the drain electrode of thetransistors is connected to the allocated bit line B. Conversely, a "1"is stored when there is no contacting of a transistor TP or,respectively, TN with the allocated word line or, respectively, bitline.

For reading an information out, the bit lines B are first pre-charged.This ensues with the assistance of the precharging transistors TV towhich a pre-charging signal PC for the n-channel transistors and aninverted signal PC' for the p-channel transistors is applied. Thepre-charging transistors TV are thereby activated. The bit-lines B towhich p-channel storing transistors are connected are recharged to avoltage VSS plus UTP, whereby UT is the threshold voltage of thep-channel transistors. Correspondingly, the bit lines to which n-channelstoring transistors TN are connected are recharged to the voltageVDD-UTN, whereby UTN is the threshold voltage of the n-channeltransistors. Subsequently, a word line W is driven with a selectionsignal and, when a "0" is stored, the allocated bit line is rechargedtoward the supply potential VDD or, respectively, VSS. For example, thep-channel transistor TP1 stores a binary "0". When it is driven by asignal on the word line WN+1, then it recharges the bit line Bn+2 towardVDD. The corresponding case applies for the n-channel transistor TN1that discharges the bit line Bn toward VSS. In this operating mode, thestoring transistors TP and TN are not operated in the source followermode.

When, by contrast, a binary "1" is read out, then the storing transistorTP or, respectively, TN is not contacted and the bit line remains at thepotential to which it had been pre-charged by the pre-chargingtransistors TV.

The read-out of the potential on the bit lines B ensues via selectiontransistors TWP or, respectively, TWN. A bit line selection signal Y isapplied to these selection signals, the transistors being activated as aresult thereof. Given bit lines to which p-channel storing transistorsTP are connected, p-channel transistors are employed as selectiontransistors; given bit lines to which n-channel storing transistors TNare connected, n-channel selection transistors TWN are employed.

The p-channel selection transistors TWP are interconnected to form agroup in a node K1. The analogous case applies for the n-channelselection transistors TWN; they are interconnected in a node K2. Apre-charging and holding circuit VL1, HL1, is connected to the node K1and a precharging circuit VL2 and holding circuit HL2 is connected tothe node K2. The node K1, K2 is pre-charged to the potential VSS or VDDwith the pre-charging circuit VL1, VL2, namely with the assistance of apre-charging transistor TL1, TL2 that is likewise drive with thepre-charging signal PC, PC'. Corresponding to the potential on one ofthe bit lines, the node K1, K2 is re-charged or is not re-charged afterthe drive of the selection transistors TW. The node K1, K2 thus assumesthe potential on the read-out bit line. This potential is maintainedwith the assistance of the holding circuit HL1, HL2. This is especiallyimportant when a "1" is read out. The transistors TH of the holdingcircuit HL1, HL2 are then activated and apply a fixed potential VSS or,respectively, VDD minus UTN to the node K1, or, respectively, K2.

The output circuit containing the selection transistors TW, thepre-charging circuit VL and the holding circuit HL further comprisestristate driver circuits TR via which the signal at the output of theholding circuit HL is transmitted to the data line DA. The tristatecircuit TR is selected with the assistance of a decoder signal EN.

When, for example, an information is to be read out that is stored inthe p-channel storing transistor TP2, then the pre-charging signal PC'is applied and, thus, the bit line Bn+3 is pre-charged to VSS+ UTP;correspondingly, the node K1 is re-charged to VSS via the transistorTL1. After this recharging, the pre-charging signal PC disappears andthe word line Wn+1 is driven. Since the transistor TP2 is not contactedwith the bit line Bn+3, the potential on the bit line does not change.By applying an inverted selection signal Y', the selection transistorTWP becomes activated and connects the bit line Bm+3 to the node K1.Slight charge sharing between the bit line Bm+3 (potential VSS+ UTP) andthe node K1 (potential VSS) does not lead to the triggering of thefollowing inverter since the transistors of the holding circuit HL1 areactivated. The read-out information is transmitted to the data line viathe tristate circuit TR by applying the decoder signal EN.

When, by contrast, an information is to be read out from the p-channeltransistor TP1, then the bit line Bm+2 that is initially pre-charged toVSS plus UTP is re-charged toward VDD by the transistor TP1. Thepotential thereby arising is applied to the node K1 via the selectiontransistor after the application of the bit line selection signal Y' andlikewise leads to the re-charging thereof. The potential at the node K1is then transmitted to the data line DA via the tristate circuit TRafter the application of the decoder signal EN.

In FIG. 1, VDD references a first operating potential, VSS references asecond operating potential, PC references the pre-charging signal, PC'references the inverted pre-charging signal, Y references the bit lineselection signal, Y' references the inverted bit line selection signal,EN references the decoder output signal and EN' references the inverteddecoder output signal. A contacting between the gate electrode of astoring transistor with a word line is present when the gate electrodeis marked with a small circle. The analogous case applies for the drainelectrode of the storing transistors. The gate electrode is referencedG, the source electrode is referenced S and the drain electrode D.

The exemplary embodiment of FIG. 2 differs from that of FIG. 1 only inthat the allocation of the p-channel storing transistors to theinformation to be stored is inverted. Now, a contacted p-channel storingtransistors, for example, TP1, stores a "1"; a non-contacted p-channel,storing transistor, for example TP2, stores a "0". In comparison to theexemplary embodiment of FIG. 1, positive logic is employed in thep-channel storing transistors TP. Accordingly, the allocated tristatecircuit TR is executed inverted.

The layout of a basic cell GZ comprising three p-channel transistors TPand three n-channel transistors TN and an additional n-channeltransistor TZ is shown in FIG. 3. The p-channel transistors TP1 throughTP3 are arranged in a first region BR1. A second region BR2 in which then-channel transistors TN1 through TN3 lie is adjacent to the firstregion BR1. The p-channel transistors TP and the n-channel transistorsTN have their controlled paths lying in series; the gate electrodes Gare arranged parallel to one another. Their gate terminals GTA arearranged between the two regions BR1 and BR2 or lie at the inner edgesof these regions. The one supply potential VDD is arranged at the outeredge of the first region BR1 and the other supply potential VSS isarranged at the outer edge of the other region BR2. The n-channeltransistors TN lie in a p-well PW. Further, a well contact WKD and asubstrate contact SKT are provided.

The basic cell GZ also contains an additional n-channel transistor TZthat lies in the proximity of the second supply potential VSS adjacentto the second region BR2. The gate electrodes of the p-channeltransistor TP3 and of the n-channel transistor TN3 are connected to oneanother.

The two p-channel transistors TP1 and TP2 and the two n-channeltransistors TN1 and TN2 of the basic cell are employed for therealization of a read-only memory. Corresponding to the exemplaryembodiment of FIG. 1 and of FIG. 2, four information can thus be stored.To that end, contactings of the transistor electrodes to the word line Wand to the bit line must be carried out or not be carried outcorresponding to FIG. 1 or FIG. 2. The word lines W1 and W2 therebyproceed over both regions BR1 and BR2; namely, the word line W1 liesbetween the transistors TP1 or, respectively, TN1 and TP3 or,respectively, TN3; the word line W2 is conducted adjacent to the gateelectrode of the transistor TP2 and TN2 over the diffusion region at theedge of the regions BR1 and BR2. A shunt line UL1 that runs along at theinside edge of the region BR1 is provided for contacting the word lineW1 to the gate electrodes G of the p-channel transistors TP1 and TP2. Asecond shunt line UL2 that runs along at the inside edge of the secondregion BR2 is provided for contacting the word line W2 to the n-channeltransistors TN1 and TN2.

The bit lines B1 through B4 proceed perpendicularly relative to the wordlines W, whereby every bit line B can be contacted only to one of thetransistors of the basic cell GZ. The bit line B1 is contactible to thedrain electrode of the n-channel transistors TN2; the bit line B2 iscontactible to the drain electrode of the n-channel transistors TN1; thebit line B3 is contactible to the drain electrode of the p-channeltransistors TP1; and the bit line B4 is contactible to the drainelectrode of the p-channel transistor TP2. The layout of the transistorsof the basic cell is executed such that the bit lines B3 and B4 proceedover the region BR1, the bit line B1 proceeds over the region BR2, andthe bit line B2 proceeds over the space between the two region BR1 andBR2. The connection of the p-channel transistors TP1 and TP2 to thesupply potential VDD ensues between the gate electrodes of thetransistors TP1 and TP3 or, respectively, TP2 and TP3 and,correspondingly, the connection of the n-channel transistors TN1 and TN2to the supply potential VSS proceeds between the gate electrodes of thetransistors TN1 and TN3 or, respectively, TN2 and TN3.

The additional transistor TZ is not utilized for storing information inthe read-only memory; for example, it can be deactivated and can haveits gate electrode connected to the supply potential VSS. However, itcan be employed as transistor TH in the holding circuits. To that end,it is beneficial that it has a small channel width. The transistors TT,TN cannot be used for that purpose because, for example, the p-channeltransistor TR1 could not trigger the node K1 that is pre-charged to VSSupon read-out of a "1" from TP1. The node K1, namely, is held at VSS bythe holding circuit HL1 and must be triggered by TP1.

FIG. 4 shows a further exemplary embodiment of the read-only memory uponemployment of the basic cells of FIG. 3. The difference compared to theembodiments of FIG. 2 and of FIG. 1 is comprised therein that four wordlines Wn through Wn+3 and two bit lines Bm through Bm+1 are now used perbasic cell. The two p-channel translators TP1 and TP2 that are used forstoring now lie at one line, namely, the bit line Bm+1; correspondingly,the two n-channel transistors TN1 and TN2 used for storing lie at onebit line Bm. The storing of the information ensues in accord with FIG. 1and the operating mode is also comparable to that set forth withreference thereto.

FIG. 5 corresponds to FIG. 2 with the difference that four word lines Wnthrough Wn+3 and only two bit lines Bm and Bm+1 are again provided here.The pre-charging transistors TV and the selection transistors TW areoperated in accord with FIG. 1 and FIG. 2. The analogous case applies tothe output circuit AG that is not shown in FIGS. 4 and 5.

A read-only memory wherein work is carried out without a pre-chargingcan be derived from FIG. 6. It has the advantage that the cycle time isidentical to the read time as a consequence of the pre-charging of thebit lines Bm, Bm+1 that is not required here. A disadvantage of thiscircuit is that only two bits can be stored in a basic cell since arespective p-channel transistor and a respective n-channel transistorare required for a bit. The programming again ensues by the contactingof the corresponding gate electrodes and drain electrodes. Theinformation is written onto a data line DA via the read amplifier LV viatwo transfer gates TG that are driven by an address decoder. Forexample, the n-channel transistor TN2 is contacted to a word line Wn andto a bit line Bm+1 for storing a "0", whereas the p-channel transistorTP2 is not contacted. For storing a "1", by contrast, the p-channeltransistor TP1 is contacted to the bit line Bm and to the word line Wn,whereas the n-channel transistor Tn is not contacted. One of the bitlines Bm or Bm+1 is selected with the assistance of the bit lineselection signal Ym or Ym+1 and, given the additional presence of asignal from the address decoder, is connected through to the readamplifier LV.

For realizing a read-only memory composed of basic cells GZ, these arearranged in rows and columns, corresponding to a portion of FIG. 7.Since every basic cell GZ can store four information or, in accord withFIG. 6, two information, a read-only memory of arbitrary size can berealized with a corresponding plurality of basic cells. The outputcircuit and pre-charging transistors required for the operation of theread-only memory can likewise be realized with the assistance of thebasic cells GZ. FIG. 7 thereby only shows the arrangement of the basiccells GZ, but not their wiring.

The invention is not limited to the particular details of the apparatusdepicted and other modifications and applications are contemplated.Certain other changes may be made in the above described apparatuswithout departing from the true spirit and scope of the invention hereininvolved. It is intended, therefore, that the subject matter in theabove depiction shall be interpreted as illustrative and not in alimiting sense.

What is claimed is:
 1. Read-only memory for a gate array arrangementhaving basic cells that contain at least one n-channel transistor andone p-channel transistor, comprising:a) for each basic cell of the gatearray arrangement, a1) the p-channel transistors each have their gateelectrode connectible to a first selection line that is connected to afirst potential for the selection of the p-channel transistors, havetheir source electrode connected to a first supply potential and havetheir drain electrode connectible to a bit line, a2) the n-channeltransistors have their gate electrode connectible to a second selectionline that is connected to a second potential for the selection of then-channel transistors, have their source electrode connected to a secondsupply potential and have their drain electrode connectible respectivelyto a bit line of a plurality of bit lines for storing information; b) anoutput circuit connecting the plurality of bit lines to a data line, b1)said output circuit having, per bit line, a selection transistor of aplurality of selection transistors or respectively, that is driven by abit line selection signal connected to the bit line and having the sameconductivity type as the associated n-channel or p-channel transistorsemployed for information storing, said selection transistor beingconnected to selection transistors of the same conductivity type ingroups in a node of the output circuit, b2) said output circuitcontaining a pre-charging circuit and a holding circuit per group ofselection transistors of one conductivity type, said output circuitbeing connected to the node and, before the drive of the selectiontransistors by a bit line selection signal, this node is charged to thesupply potential, or respectively, used for the pre-charging of the bitline and holding the information potential at the node after theread-out of the information.
 2. Read-only memory according to claim 1,wherein the bit lines to which the p-channel transistors are connectibleare connected to the second supply potential via a p-channel transistorthat is driven by a first pre-charging signal.
 3. Read-only memoryaccording to claim 2, wherein the bit lines to which the n-channeltransistors are connectible are connected to the first supply potentialvia a n-channel transistor driven by a second pre-charging signal. 4.Read-only memory according to claim 3, wherein the pre-charging circuitcomprises a transistor driven by the pre-charging signal, saidtransistor re-charging the node to a potential to which the allocatedbit line is pre-charged.
 5. Read-only memory according to claim 4,wherein the output circuit contains a tristate circuit that connects theoutput of the holding circuit to the data line.
 6. Read-only memoryaccording to claim 3, wherein the n-channel transistors are connected tothe allocated bit line and to the allocated selection line for storingthe information of the one type ("0") and the p-channel transistors areconnected to the allocated bit line and to the allocated selection linefor storing the information of the other type ("1").
 7. Read-only memoryaccording to claim 6, wherein the basic cell contains respectively threep-channel transistors and three n-channel transistors whose controlledpaths are respectively connected in series; and wherein the informationare stored in outer transistors thereof.
 8. Read-only memory accordingto claim 7, wherein the basic cell is composed of three p-channeltransistors arranged in a first region, of three n-channel transistorsarranged in a second region lying adjacent to said first region, and ofan additional n-channel transistor lying next to said second region;wherein the terminals for the gate electrodes of the n-channel andp-channel transistors lie between the first and second regions or at theinside edges thereof and the line of the first supply potential proceedsat the outer edge of the first region, and the line for the secondsupply potential proceeds at the outer edge of the second region; andwherein the additional n-channel transistor has its gate terminal lyingadjacent to the line for the second potential.
 9. Read-only memoryaccording to claim 8, wherein a first selection line proceeds betweenthe gate electrodes of the one outer transistor and the middletransistors; wherein a second selection line proceeds next to the gateelectrode of the other, outwardly disposed transistor at the edge of thefirst and second regions; and wherein the contacting of the firstselection line to the gate electrodes of the p-channel transistorsensues via a shunt line connected at the inner edge of the first regionand the contacting to the gate electrodes of the n-channel transistorsensues via a second shunt line proceeding at the inner edge of thesecond region; wherein two bit lines proceed transversely relative tothe word lines over the first region for contacting the drain electrodesof the p-channel transistors in the first region; wherein a bit lineproceeds transversely relative to the selection lines over the secondregion adjacent to the inner edge thereof and a second bit line proceedstransversely relative to the selection lines between the first andsecond region for contacting the drain electrodes of the n-channeltransistors in the second region.
 10. Read-only memory according toclaim 9, wherein the contacting of the drain terminals of the n-channeland p-channel transistors to the bit lines ensues at the edge of thefirst and second regions, whereas the contacting of the source terminalsto the first and second supply potentials ensues in the space betweenthe gate electrodes of the outer transistors and the middle transistors.11. Read-only memory according to claim 8, wherein the gate terminal ofthe additional n-channel transistors is connected to the second supplypotential.
 12. Read-only memory according to claim 11, wherein thetransistors of the holding circuits are composed of additionaltransistors of the basic cell.